`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/12/01 18:54:30
// Design Name: 
// Module Name: test1011
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module test1011

(
    input rst,
    input clk,
    input x,
    output reg out
);

parameter s0='b00,s1='b01,s2='b10,s3='b11;
reg [1:0] state;
reg [1:0] next_state;

always @(*) begin
    if (!rst) out<=0;
    else begin
        if (x==1 && state==s3) out=1;
        else out<=0;
    end
end

always @(*) begin
    if (!rst) state=s0;
    else state=next_state;
end

always @(posedge clk) begin
    case(state)
            s0:if (x) next_state<=s1;
                else next_state<=s0;
            s1:if (x) next_state<=s1;
                else next_state<=s2;
            s2:if (x) next_state<=s3;
                else next_state<=s0;
            s3:if (x) next_state<=s1;
                else next_state<=s2;
    endcase
end
endmodule
